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gaas, phemt, mmic, single positive supply, d c to 7.5 g hz, 1 w power amplifier data sheet hmc637bpm5e rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is a ssumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2018 analog devices, inc. all rights reserved. technical support www.analog.com features p1db output power: 28 dbm typical gain: 15.5 db typical o utput ip3: 39 dbm typical self biased at v dd = 12 v a t 3 4 5 ma typical o ptional bias control on v gg 1 for i dq adjustment o ptional bias control on v gg 2 for ip2 and ip3 optimization 50 ? m atched i nput/ o utput 32- lead, 5 mm 5 mm lfcsp package : 25 mm 2 applications military and s pace test i nstrumentation functional block dia gram 17 1 3 4 2 9 gnd v gg 2 nic gnd 5 6 rfin gnd 7 nic 8 gnd gnd p ackage base gnd 18 nic 19 nic 20 gnd 21 rfout/v dd 22 gnd 23 nic 24 gnd gnd 12 nic 1 1 nic 10 nic 13 v gg 1 14 nic 15 acg3 16 gnd 25 gnd 26 nic 27 nic 28 nic 29 acg2 30 acg1 31 nic 32 gnd 16273-001 figure 1. general description the hmc637bpm5e is a gallium arsenide ( gaas ), monolithic microwave integrated circuit (mmic), pseudomorphic high electron mobility transistor ( phemt ) , casc o de d istributed p ower a mplifier . the device is s elf biased in normal operation and features optional bias control for quiescent current ( i dq ) a djustment and for second - order intercept ( ip2 ) and third - order intercept ( ip3 ) optimization . the amplifier operates from dc to 7.5 ghz , providing 15.5 db of small signal gain, 28 dbm output power at 1 db gain compression, a typical o utput ip3 of 39 dbm , and a 3.5 db noise figure , while requiring 3 45 ma from a 12 v s upply voltage (v dd ). gain flatness is excellent from dc to 7.5 ghz a t 0.5 db typical , making the hmc637bpm5e ideal f or military, space , and test equipment applications. t he hmc637bpm5e also features inputs/outputs (i/os) t hat are internally matched to 50 ?, housed in a roh s - compliant, 5 mm 5 mm , premolded cavity, lead frame chip scale package ( lfcsp ) , making the device compatible with high volume , surface - mount tech nology (smt) assembly equipment.
hmc637bpm5e data sheet rev. 0 | page 2 of 21 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 frequency range = dc to 7.5 ghz ........................................... 3 absolute maximum ratings ............................................................ 4 ther mal resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 interface schematics .....................................................................6 typical performance characteristic ................................................7 theory of operation ...................................................................... 17 applications information .............................................................. 18 typical application circuit ....................................................... 19 evaluation pcb ............................................................................... 20 bill of materials ........................................................................... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 5 /2018 revision 0 : initial version
data sheet h mc637bpm5e rev. 0 | page 3 of 21 specifications frequency range = dc to 7.5 gh z t a = 25 c , v dd = 12 v , i dq = 3 45 ma , v gg 1 = gnd , v gg 2 = open , for nominal self biased operation, unless otherwise noted. table 1 . parameter symbol min typ max unit test conditions/comments frequency range dc 7.5 ghz gain 12.5 15.5 db gain flatness 0.5 db gain variation over temperature 0.015 db/c noise figure 3.5 db return loss input 15 db output 15 db output output power for 1 db compression p1db 25 28 dbm saturated output power p sat 30.5 dbm output third - order intercept ip3 39 dbm measurement taken at output power ( p out )/ tone = 10 dbm supply current i dq 345 ma for the external bias condition, adjust the gate bias voltage ( v gg 1 ) between ? 2 v up to + 0.5 v to achieve the desired quiescent current ( i dq ) voltage v dd 8 12 13 v
hmc637bpm5e data sheet rev. 0 | page 4 of 21 absolute maximum rat ings table 2 . parameter 1 rating drain bias voltage (v dd ) 14 v gate 1 voltage ( v gg 1 ) ? 2 v to +1 v gate 2 voltage ( v gg 2 ) 3.5 v to 7 v radio frequency ( rf ) input power (rfin) 25 dbm conti nuous power dissipation ( p diss ), t = 85c (derate 63.29 mw/c above 85c) 5.7 w output load voltage standing wave ratio ( vswr ) 7:1 storage temperature range ?65c to +150c operating temperature range ?55 c to +85c maximum peak reflow temperature 260c esd sensitivity human body model (hbm) class 1 c junction temperature to maintain 1 million hour mean time to failure ( mttf ) 175c nominal junction temperature (t = 85c, v dd = 12 v) 148.52c 1 when referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed . for full pin names of the multifunction pins, refer to the pin configuration and function descriptions section. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating on ly; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliab ility. thermal resistance thermal performance is directly linked to printed circuit board (pcb) design and operating environment. careful attention to pcb thermal design is required. j c is the junction to case thermal resistance. table 3 . thermal resistance package jc unit cg -32- 2 1 15.8 c/w 1 thermal impedance simulated values are based on a jedec 2s2p thermal test board with 36 thermal vias. see jedec jesd51. esd caution
data sheet h mc637bpm5e rev. 0 | page 5 of 21 pin configuration an d function descripti ons 17 1 3 4 2 9 gnd v gg 2 nic gnd 5 6 rfin gnd 7 nic 8 gnd gnd 18 nic 19 nic 20 gnd 21 rfout/v dd 22 gnd 23 nic 24 gnd notes 1. exposed p ad. the exposed p ad must be connected t o rf/dc ground. 2. nic = not internal l y connected. gnd 12 nic 1 1 nic 10 nic 13 v gg 1 14 nic 15 acg3 16 gnd 25 gnd 26 nic 27 nic 28 nic 29 acg2 30 acg1 31 nic 32 gnd hmc637bpm5e t o p view (not to scale) 16273-002 figure 2. pin configuration table 4 . pin function descriptions pin o. mnemonic description 1, 4, 6, 8, 9, 16 , 17, 20, 22, 24, 25, 32 gnd ground. these pins and the exposed pad must be connected to rf/dc ground. 2 v gg 2 gate control 2 for the amplifier. v gg 2 is left open for self biased mode. adjusting the voltage controls the gain response. external capacitors are required (see figure 69 ). see figure 7 for the interface schematic. 3, 7, 10 to 1 2, 14 , 18, 19, 23, 26 to 28, 31 ni c not internally connected. these pins must be connected to rf/dc ground. 5 rfin r f input . this pin is dc - coupled and matched to 50 ?. see figure 6 for the interface schematic. 13 v gg 1 optional gate control for the amplifier . if this pin is grounded , the amplifier runs i n self biased mode at the stan dard current of 3 45 ma . adjusting the voltage above or below the ground potential controls the drain current. external capacitors are required (see figure 69 ). see figure 8 for the interface schematic. 15 , 29, 30 acg1, acg2, acg3 low frequency termination . external bypass capacitor s are required on these pins (see figure 69). see figure 4 and figure 5 for the interface schematic s . 21 rfout/v dd rf output for the amplifier (rfout) . drain bias voltage (v dd ). connect the dc bias (v dd ) network to provide the drain current, i dd (see figure 69 ). see figure 5 for the interface schematic. epad exposed pad. the exposed pad must be connected to rf/dc ground.
hmc637bpm5e data sheet rev. 0 | page 6 of 21 interface schematics gnd 16273-003 figure 3 . gnd interface schematic rfin acg3 16273-004 4 3 acg1 rfout/v dd acg2 16273-005 5 1 2 16273-006 rfin fe 6. rfin iteace scematc acg2 vdd rfout/v dd 16273-007 7 2 v gg 1 16273-008 8 1
data sheet h mc637bpm5e rev. 0 | page 7 of 21 typical performance characteristic C25 C20 C15 C10 C5 0 5 10 15 20 0 1 2 3 4 5 6 7 8 9 10 response (db) frequenc y (ghz) s 1 1 s21 s22 16273-009 figure 9 . gain and return loss response vs. frequency, self biased mode, v dd = 12 v, v gg 1 = gnd, v gg 2 = open 8 9 10 1 1 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 gain (db) frequenc y (ghz) 8v 9v 10v 1 1v 12v 13v 16273-010 10 1 2 8 9 10 1 1 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 gain (db) frequenc y (ghz) 4v 5v (self biased) 6v 16273-0 1 1 11 2 12 1 8 9 10 1 1 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 gain (db) frequenc y (ghz) C5 5 c +2 5 c +8 5 c 16273-012 12 12 1 2 8 9 10 1 1 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 gain (db) frequenc y (ghz) 345m a (self biased) 250m a 300m a 350m a 400m a 450m a 16273-013 13 12 2 1 C20 C15 C10 C5 0 0 1 2 3 4 5 6 7 8 return loss (db) frequenc y (ghz) C5 5 c +2 5 c +8 5 c 16273-014 14 12 1 2
hmc637bpm5e data sheet rev. 0 | page 8 of 21 C20 C15 C10 C5 0 0 1 2 3 4 5 6 7 8 return loss (db) frequenc y (ghz) 8v 9v 10v 1 1v 12v 13v 16273-015 figure 15 . input return loss vs. frequency for various supply voltages (v dd ), self biased mode, v gg 2 = open, v gg 1 = gnd C20 C15 C10 C5 0 0 1 2 3 4 5 6 7 8 return loss (db) frequenc y (ghz) 4v 5v (self biased) 6v 16273-016 16 2 12 1 C20 C15 C10 C5 0 0 1 2 3 4 5 6 7 8 return loss (db) frequenc y (ghz) 8v 9v 10v 1 1v 12v 13v 16273-017 17 2 5 2 1 C20 C15 C10 C5 0 0 1 2 3 4 5 6 7 8 return loss (db) frequenc y (ghz) 345m a (self biased) 250m a 300m a 350m a 400m a 450m a 16273-018 18 12 2 1 C20 C15 C10 C5 0 0 1 2 3 4 5 6 7 8 return loss (db) frequenc y (ghz) C5 5 c +2 5 c +8 5 c 16273-019 19 12 2 1 C20 C15 C10 C5 0 0 1 2 3 4 5 6 7 8 return loss (db) frequenc y (ghz) 345m a (self biased) 250m a 300m a 350m a 400m a 450m a 16273-020 20 12 2 1
data sheet h mc637bpm5e rev. 0 | page 9 of 21 frequenc y (ghz) C20 C15 C10 C5 0 0 1 2 3 4 5 6 7 8 return loss (db) 4v 5v (self biased) 6v 16273-021 figure 21 . output return loss vs. frequency for vari ous v gg 2 values, v dd = 12 v, v gg 1 = gnd 0 2 4 6 8 10 12 14 16 0 0.02 0.04 0.06 0.08 0.10 noise figure (db) frequenc y (ghz) C5 5 c +2 5 c +8 5 c 16273-022 22 12 2 1 12 16 20 24 28 32 0 1 2 3 4 5 6 7 8 p1db (dbm) frequenc y (ghz) C5 5 c +2 5 c +8 5 c 16273-023 23 1 12 2 1 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 1 2 3 4 5 6 7 8 isol a tion (db) frequenc y (ghz) 16273-024 C5 5 c +2 5 c +8 5 c fe 24 . reee iolato . feec o vao tempeate, sel baed mode, v dd = 12 v, v gg 2 = ope, v gg 1 = gnd 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 noise figure (db) frequenc y (ghz) C5 5 c +2 5 c +8 5 c 16273-025 25 12 2 1 8 12 16 20 24 28 32 0 1 2 3 4 5 6 7 8 p1db (dbm) frequenc y (ghz) 8v 9v 10v 1 1v 12v 13v 16273-026 26 1 2 1
hmc637bpm5e data sheet rev. 0 | page 10 of 21 8 12 16 20 24 28 32 0 1 2 3 4 5 6 7 8 p1db (dbm) frequenc y (ghz) 345m a (self biased) 250m a 300m a 350m a 400m a 450m a 16273-027 figure 27 . p1db vs. frequency for various supply currents (i dd ), externally biased mode, v dd = 12 v, v gg 2 = open, controlled v gg 1 18 20 22 24 26 28 30 32 34 0 1 2 3 4 5 6 7 8 p s a t (dbm) frequenc y (ghz) C5 5 c +2 5 c +8 5 c 16273-028 28 12 2 1 18 20 22 24 26 28 30 32 34 0 1 2 3 4 5 6 7 8 p sa t (dbm) frequenc y (ghz) 345m a (self biased) 250m a 300m a 350m a 400m a 450m a 16273-029 29 12 2 1 8 12 16 20 24 28 32 0 1 2 3 4 5 6 7 8 p1db (dbm) frequenc y (ghz) 4v 5v (self-biased) 6v 16273-030 30 1 2 12 1 18 20 22 24 26 28 30 32 34 0 1 2 3 4 5 6 7 8 p s a t (dbm) frequenc y (ghz) 8v 9v 10v 1 1v 12v 13v 16273-031 31 2 1 18 20 22 24 26 28 30 32 34 0 1 2 3 4 5 6 7 8 p s a t (dbm) frequenc y (ghz) 4v 5v (self biased) 6v 16273-032 32 2 12 1
data sheet h mc637bpm5e rev. 0 | page 11 of 21 0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 8 p ae (%) frequenc y (ghz) C5 5 c +2 5 c +8 5 c 16273-033 figure 33 . power added efficiency (pae) vs. frequency for various temperatures, self biased mode, v dd = 12 v, v gg 2 = open, v gg 1 = gnd, pae measured at p sat 0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 8 p ae (%) frequenc y (ghz) 345m a (self biased) 250m a 300m a 350m a 400m a 450m a 16273-034 34 12 2 1 330 345 360 375 390 405 420 435 0 5 10 15 20 25 30 35 0 2 4 6 8 10 12 14 16 18 20 i dd (ma) p out (dbm), gain (db), p ae (%) input power (dbm) p out gain p ae i dd 16273-035 35 1 12 1 2 0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 8 p ae (%) frequenc y (ghz) 8v 9v 10v 1 1v 12v 13v 16273-036 36 2 1 0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 8 p ae (%) frequenc y (ghz) 4v 5v (self biased) 6v 16273-037 37 2 12 1 330 345 360 375 390 405 420 435 0 5 10 15 20 25 30 35 0 2 4 6 8 10 12 14 16 18 20 i dd (ma) p out (dbm), gain (db), p ae (%) input power (dbm) p out gain p ae i dd 16273-038 38 3 12 1 2
hmc637bpm5e data sheet rev. 0 | page 12 of 21 0 5 10 15 20 25 30 35 0 2 4 6 8 10 12 14 16 18 20 p out (dbm), gain (db), p ae (%) input power (dbm) 330 345 360 375 390 405 420 435 i dd (ma) p out gain p ae i dd 16273-039 figure 39 . p out , gain, pae , and i dd vs. input power, 6 ghz, v dd = 12 v, v gg 1 = gnd, v gg 2 = open 10 15 20 25 30 35 40 45 0 1 2 3 4 5 6 7 8 output ip3 (dbm) frequenc y (ghz) C5 5 c +2 5 c +8 5 c 16273-040 40 3 10 12 2 1 10 15 20 25 30 35 40 45 0 1 2 3 4 5 6 7 8 output ip3 (dbm) frequenc y (ghz) 345m a (self biased) 250m a 300m a 350m a 400m a 450m a 16273-041 41 3 12 2 1 10 0 1 2 3 4 5 6 0 4 8 12 16 20 power dissi pa tion (w) input power (dbm) 1ghz 2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 16273-042 maximum p diss fe 42 . poe dpato . ipt poe at t a = 85c, v dd = 12 v, v gg 1 = gnd, v gg 2 = ope 10 15 20 25 30 35 40 45 0 1 2 3 4 5 6 7 8 output ip3 (dbm) frequenc y (ghz) 8v 9v 10v 1 1v 12v 13v 16273-043 43 3 2 1 10 10 15 20 25 30 35 40 45 0 1 2 3 4 5 6 7 8 output ip3 (dbm) frequenc y (ghz) 4v 5v (self biased) 6v 16273-044 figure 44. ou tput ip3 vs. frequency for variou s v gg 2 values, v dd = 12 v, v gg 1 = gnd, p out /tone = 10 dbm
data sheet h mc637bpm5e rev. 0 | page 13 of 21 10 15 20 25 30 35 40 45 0 1 2 3 4 5 6 7 8 output ip3 (dbm) frequenc y (ghz) 0dbm 10dbm 20dbm 16273-045 figure 45 . o utput ip3 vs. frequency for various p out /tone, v dd = 12 v, v gg 2 = open, v gg 1 = gnd 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 im3 (dbc) p out /t one (dbm) 1ghz 2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 16273-046 46 - 3 9 2 1 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 im3 (dbc) p out /t one (dbm) 1ghz 2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 16273-047 47 3 11 2 1 p out / t one (dbm) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 im3 (dbc) 1ghz 2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 16273-048 48 3 8 2 1 p out /t one (dbm) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 im3 (dbc) 1ghz 2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 16273-049 49 3 10 2 1 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 im3 (dbc) p out / t one (dbm) 1ghz 2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 16273-050 50 3 12 2 1
hmc637bpm5e data sheet rev. 0 | page 14 of 21 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 im3 (dbc) p out / t one (dbm) 16273-051 1ghz 2ghz 3ghz 4ghz 5ghz 6ghz 7ghz figure 51 . im3 vs. p out /tone, v dd = 13 v, v gg 2 = open, v gg 1 = gnd 0 10 20 30 40 50 60 0 1 2 3 4 5 6 7 8 output ip2 (dbm) frequenc y (ghz) 8v 9v 10v 1 1v 12v 13v 16273-052 52 2 2 1 10 10 15 20 25 30 35 40 45 50 55 60 0 1 2 3 4 5 6 7 8 output ip2 (dbm) frequenc y (ghz) 4v 5v (self biased) 6v 16273-053 53 2 2 12 1 10 0 10 20 30 40 50 60 0 1 2 3 4 5 6 7 8 output ip2 (dbm) frequenc y (ghz) C5 5 c +2 5 c +8 5 c 16273-054 54 2 10 12 2 1 0 10 20 30 40 50 60 70 0 1 2 3 4 5 6 7 8 output ip2 (dbm) frequenc y (ghz) 345m a (self biased) 250m a 300m a 350m a 400m a 450m a 16273-055 55 2 12 2 1 10 0 10 20 30 40 50 60 0 1 2 3 4 5 6 7 8 output ip2 (dbm) frequenc y (ghz) 0dbm 10dbm 20dbm 16273-056 56 2 12 2 1
data sheet h mc637bpm5e rev. 0 | page 15 of 21 0 10 20 30 40 50 60 1 2 3 4 5 6 7 8 second harmonic (dbc) frequenc y (ghz) C5 5 c +2 5 c +8 5 c 16273-057 figure 57 . second harmonic vs. frequency for various temperatures, p out = 10 dbm, v dd = 12 v, v gg 2 = open, v gg 1 = gnd (self biased) 0 10 20 30 40 50 60 1 2 3 4 5 6 7 8 second harmonic (dbc) frequenc y (ghz) 345m a (self biased) 250m a 300m a 350m a 400m a 450m a 16273-058 58 12 2 1 10 0 10 20 30 40 50 60 1 2 3 4 5 6 7 8 second harmonic (dbc) frequenc y (ghz) 10dbm 12dbm 14dbm 16dbm 18dbm 20dbm 22dbm 24dbm 16273-059 59 12 2 1 0 10 20 30 40 50 60 1 2 3 4 5 6 7 8 second harmonic (dbc) frequenc y (ghz) 8v 9v 10v 1 1v 12v 13v 16273-060 60 10 2 1 0 10 20 30 40 50 60 1 2 3 4 5 6 7 8 second harmonic (dbc) frequenc y (ghz) 4v 5v (self biased) 6v 16273-061 61 2 12 1 10 300 325 350 375 400 425 450 475 500 0 4 8 12 16 20 i dd (ma) input power (dbm) 1ghz 2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 16273-062 62 12 2 1
hmc637bpm5e data sheet rev. 0 | page 16 of 21 C0.20 C0.16 C0.12 C0.08 C0.04 0 0.04 0.08 0.12 0.16 0.20 0 4 8 12 16 20 i gg 1 (ma) input power (dbm) 1ghz 2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 16273-063 figure 63 . gate 1 current (i gg 1 ) vs. input power for various frequencies, v dd = 12 v, v gg 2 = open, v gg 1 = gnd C75 0 75 150 225 300 375 450 525 C1.50 C1.25 C1.00 C0.75 C0.50 C0.25 0 0.25 0.50 i dd (ma) v gg 1 (v) 16273-064 64 1 12 2 16273-065 300 310 320 330 340 350 360 370 380 390 400 4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00 i dd (ma) v gg2 (v) fe 65 . i dd . v gg 2, v dd = 12 v, v gg 1 = gnd C2.0 C1.5 C1.0 C0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 4 8 12 16 20 i gg2 (ma) input power (dbm) 1ghz 2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 16273-066 66 2 2 12 2 5 1 300 310 320 330 340 350 360 370 380 390 400 8 9 10 1 1 12 13 i dd (ma) v dd (v) 16273-067 67 2 1
data sheet h mc637bpm5e rev. 0 | page 17 of 21 theory of operation the hmc637bpm5e is a gaas , mmic, phemt, casco de distrib - uted power amplifier. the cascode distributed architecture of the hmc637bpm5e uses a fundamental cell consisting of a stack of two field effect transistors (fets) with the source of the upper fet connected to the drain of the lower fet. the fundamental cell is then duplicated several times with an rfin transmission line interconnecting the gates of the lower fets and an rfout transmission line interconnecting the drains of the upper fets. acg2 t -line t -line rfout/ v dd acg1 acg3 v gg 1 v gg 2 rfin vdd 16273-068 figure 68 . simplified schematic of the cascode distributed amplifier additional circuit design techniques are used around each cell to optimize the overall bandwidth, output power , and noise figure. the major benefit of this architecture is that a high output level is maintained across a bandwidth far greater than what a single instance of the fundamental cell provides. a simplified schematic of this architecture is shown in figure 68. the gate bias voltages of the upper fets are set internally by a resistive voltage divider tapped off at v dd , resulting in a 5 v bias for the nominal v dd value of 12 v. however, the v gg 2 pin is provided to allow t he application of an externally generated bias voltage with in the range of 4 v up to 6 v. application of such a voltage allows adjustment of ip3 and ip2 by as much as 3 db a nd 1.5 db , respectively, while minimally affecting the gain, noise figure, p1db, p sat , and pae. the effect of this bias adjustmen t on performance is m o re apparent at lower operating frequencies. for simplified biasing without the need for a negative voltage rail, v g g 1 can be connected directly to gnd. with v dd = 12 v and v gg 1 grounded, a quiescent drain current of 345 ma (typical) result s . an externally generated v gg 1 voltage can optionally be applied, allowing adjustment of the quiescent drain current above and belo w the 345 ma nominal value . as an example, figure 64 shows that by adjusting v gg 1 from ? 0.3 v to +0.3 v (approximately), quiescent dr ain currents from 250 ma to 450 ma can be obtained. the hmc637bpm5e has single - ended input and output ports with impedances nominally equal to 50 over the dc to 7.5 ghz f requency range. therefore , the device can be directly insert ed into a 50 system with no required impedance matchin g circuitry . similarly, the input and output impedances are sufficiently stable across variations in temperature and supply voltage so that no impedance matching compensation is required. the rf output port additionally functions as the v dd bias pin, requiring an rf choke through which dc bias is applied. though the device technically operates down to dc, blocking capacitors are recommended at the rf input and output ports to prevent the stages with which they interface from loading the dc bias supplies and suffering damage. the rf choke and blocking capacitor at the rf output together constitute a bias tee. in practice, the external rf choke and dc blocking capacitor selections limit the lowest frequency of operation. acg1 through acg3 are nodes at which ac terminations (capacitors) to ground can be provided. the use of such terminations serve s to roll off th e gain at frequencies below 200 mhz, allowing the flattest possible gain response to be obtained over various frequencies. i t is critic al to supply very low inductance ground connections to the gnd pins and to the package base exposed pad to ensure stable operation. to achieve optimal performance from the hmc637bpm5e and to prevent damage to the device, do not exceed the absolute maximum ratings .
hmc637bpm5e data sheet rev. 0 | page 18 of 21 a pplications i nformation capacitive bypassing is required for v dd and v gg 1 , as shown in the typical application circuit in figure 69. both the rf in and rfout/v dd pins are dc - coupled. use of an ext ernal dc block ing c apacitor a t rfin is recommended . use of an external rf choke plus a dc blocking capacitor ( for example, a bias tee) at rfout/ v dd is required. for wideband a pplications, ensure that the frequency responses of the external biasing and blocking components are adequate for use across the e ntire frequency range of the application. the hmc637bpm5e operates in either self biased or e xternally biased mode . to operate in self biased mode , ground the v gg 1 pin and leave v gg 2 open . for the externally biased configurat ion, adjust v gg 1 within ? 2 v to +0 .5 v to set the target drain current and adjust v gg 2 from 4 v to 6 v for ip2 and ip3 control . the r ecomme nded bias sequence during power - up for self biased operation is as follows : 1. connect gnd. 2. set v dd to 12 v. 3. apply the rf signal. the r ecommended bias sequence du ring power - down for self biased operation is as follows : 1. turn off the rfin signal. 2. set v dd t o 0 v. the r ecomme nded bias sequence during power - up for externally biased operation is as follows : 1. connect gnd. 2. set v gg 1 t o ? 2 v. 3. set v dd to 12 v. 4. increase v gg 1 to achieve the desired quiescent current (i dq ). 5. apply the rf signal. 6. when using the ip2/ip3 control function, apply a voltage from 4 v to 6 v until the desired performance is obtained. the r ecomme nded bias sequence during power - down for exter nally biased operation is as follows : 1. turn off the rfin signal. 2. remove the v gg 2 voltage. 3. decrease v gg 1 to ?2 v to achieve a typical i dq of 0 ma. 4. set v dd t o 0 v. 5. set v gg 1 t o 0 v. adhere to the values shown in the absolu te maximum ratings section. unless otherwise noted, all measurements and data shown were taken using the typical application circuit (see figure 69) , and biased per the conditions in this section. the bias conditions described in this section are the operating points recommended to optimize the overall device performance. operation using other bias conditions may result in performance that differs from what is shown in the typical performance characteristic section. to obtain the best performance while avoiding damag e to the device, follow the recommended biasing sequence s described in this section.
data sheet h mc637bpm5e rev. 0 | page 19 of 21 typical application circuit in figure 69 , the drain bias (v dd ) must be applied through an external broadband bias tee co nnected at rfout/v dd and connect ed to an external dc block at rfin. optional capacitors can be used if the device is to be operated below 200 mhz. 17 1 3 4 2 9 v gg 2 5 6 rfin 7 8 18 19 20 21 rfout note 1 note 2 note 1 notes 1. drain bias (v dd ) must be applied through an eterna l bias tee connected a t the rfout/v dd pin and an externa l dc block must be connected a t the rfin pin. 2. optiona l ca p aci t ors must be used if the device is oper a ted below 200mhz. c1 1000pf c4 1000pf c5 0.01f c2 1000pf c6 0.01f c9 4.7f v dd 22 23 24 12 1 1 10 13 v gg 1 14 15 acg3 16 25 26 27 28 29 acg2 30 acg1 31 32 note 2 c8 0.01f c10 4.7f c3 1000pf c7 0.01f c1 1 4.7f 16273-069 figure 69 . typical application circuit
hmc637bpm5e data sheet rev. 0 | page 20 of 21 evaluation p cb the ev1hmc 637bpm5 (600 - 01 711- 00) evaluation pcb is shown in figure 70. bill of materials use rf circuit design techniques for the circuit board used in the application. provide 50 ? impedance for the signal lines and directly connect the package ground leads and exposed pad to the ground plane, similar to what is shown in figure 70 . use a sufficient number of via holes to connect the top and bottom ground planes , including the grounds dir ectly beneath the ground pad to provide adequate electrical and thermal conduction . use of a heat sink on the bottom side of the pcb is recommended. the evaluation pcb shown in figure 70 is available from analog devices, inc., upon request. 600-01711-00-1 ctnl gnd vgg rfin rfout thru cal gnd c11 + c4 c2 c6 c8 c3 c7 c1 c10 + + c9 c5 j1 j2 r1 j3 j4 u1 16273-070 figure 70 . evaluation pcb table 5 . bill of materials for the evaluation pcb EV1HMC637BPM5 (600 - 01 711 - 00) item description j1, j2 pcb mount k connector s j3, j4 dc pins c1, c2, c3, c4 1000 pf capacitors, 0402 package c5, c6, c7, c8 1 0 000 pf capacitors, 0402 package c 9, c10, c11 4.7 f capacitors, tantalum, 1206 package r1 0 ? resistor , 0402 package u1 hmc637bpm5e pcb 600- 01711 - 00 evaluation pcb; circuit board material: rogers 4350 or arlon 25fr
data sheet h mc637bpm5e rev. 0 | page 21 of 21 outline dimensions 04-19-2017-a 1 0.50 bsc bot t om view top view side view pin 1 indic a t or 3 2 9 16 17 24 25 8 0.30 0.25 0.20 5.10 5.00 sq 4.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 3.20 3.10 sq 3.00 pkg-005068 3.50 ref exposed p a d 1.35 1.25 1.15 0.050 max 0.035 nom 0.203 ref 0.40 0.60 ref coplanarity 0.08 se a ting plane pin 1 indic a t or area options (see detail a) detail a (jedec 95) figure 71 . 32 - lead lead f rame chip scale package, premolded cavity [lfcsp_cav] 5 mm 5 mm body and 1.25 mm package height (c g - 32 - 2) dimensions shown in millimeter ordering guide model 1 , 2 temperature msl rating 3 description 4 package option hmc637bpm5e ?55c to +85c 3 32 - lead lead frame chip scale package, premolded cavity [lfcsp_cav] cg - 32 - 2 hmc637bpm5etr ?55c to +85c 3 32- lead lead frame chip scale package, premolded cavity [lfcsp_cav] cg -32- 2 ev1hmc 637bpm5 evaluation board 1 all parts are rohs compliant. 2 when ordering the evaluation board only, reference the model number, EV1HMC637BPM5. 3 see the absolute maximum ratings section for additional information. 4 t he lead finish of the hmc637bpm5e and the hmc637bpm5etr is nickel palladium go ld (nipdau). ? 2018 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d16273 - 0 - 5/18(0)

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